bi-cmos & dmos 32bit serial-input latched driver m 566 93f p/g p mitsubishi des cri pt i o n the m56693 is a semiconductor integrated circuit that has a built- in, 32-bit shift register and a latch of cmos structure with serial input and serial/parallel output, and a 32-bit totem-pole-type parallel output driver o f high pressure proof dmos structure. employed are bi-cmos and high pressure proof dmos processing technology. f e at ures l serial input?erial/parallel output l cascade connections possible through serial output l latch circuit included for each stage l driver supply voltage: v h =120v l operating temperature: -20 ? 75 c app l i cat i o n vacuum fluorescent display anode driver f unct i o n the m56693 comprises a 32-bit d type flip-flop with a 3 2 latches connected to its output. in accordance with truth table 1, inputting data to sin and clock pulse to clk allows sin signal to be put into the internal shift register when the clock changes from ??t o ?? a n d simultaneously shift register data to be shifted sequentially. serial output sout i s used b y connecting t o the next stage m56693 sin when more than one m56693 is used to expand bits in the series. in accordance with truth table 2, parallel output allows the latch to pass data through if lat input is turned to ?? and data to b e retained if lat is turned to ?? driver output hvon allows data from the latch to be output if blk input is turned to ?? and ?? to be output if blk input is turned to ?? irrespective of data from the latch. pi n c o n f i g urat i o n ( to p v i e w ) sin sout hvo 1 hvo 2 hvo 3 hvo 4 hvo 5 hvo 6 hvo 7 hvo 8 hvo 9 hvo 10 hvo 11 34 35 36 37 38 39 40 41 42 43 44 22 21 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 v h v dd n.c lgnd clk lat v h blk pgnd hvo 22 hvo 21 hvo 20 hvo 19 hvo 18 hvo 17 hvo 16 hvo 15 hvo 14 hvo 13 hvo 12 pgnd hvo 32 hvo 31 hvo 30 hvo 29 hvo 28 hvo 27 hvo 26 hvo 25 hvo 24 hvo 23 outline 44p6n-a (fp) m5 6693 fp n.c: no connection outline 48p6d-a (gp) hvo 19 hvo 12 hvo 13 n.c 46 47 37 38 39 40 41 42 43 44 45 22 21 20 19 18 17 16 15 14 13 23 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 35 34 hvo 14 hvo 15 hvo 16 hvo 17 hvo 18 hvo 20 hvo 21 hvo 22 12 24 n.c hvo 32 hvo 31 hvo 30 hvo 29 hvo 28 hvo 27 hvo 26 hvo 25 hvo 24 hvo 23 n.c 36 48 hvo 5 hvo 6 n.c hvo 7 hvo 8 hvo 9 hvo 10 hvo 11 n.c hvo 3 hvo 4 hvo 2 pgnd v dd pgnd lgnd clk blk sout v h sin hvo 1 lat v h m5 6693 gp
bi-cmos & dmos 32bit serial-input latched driver m 566 93f p/g p mitsubishi b l oc k d ia gr a m (note : pin no. in paretheses are of m56693gp) output protect circuit 8 7 9 6 q t d q l d q t d q l d q t d q l d q t d q l d q t d q l d q t d q l d 2 42 43 41 14 13 12 blk lat sin clk sout 4 n.c 10 1 44 11 v h pgnd 5 v dd lgnd hvo 32 hvo 31 hvo 30 hvo 3 hvo 2 hvo 1 3 (12) (13) (14) (46) (47) (48) (4) (8) (7) (9) (6) (2)(10) (1)(11) (5) (3) (18)(24)(25) (37)(38) tr ut h t able 2. l a tch a n d d r iv er sect ion s hvon dn lat blk x h l x dn=nth bit dff retention data hvon=nth bit driver output l=??level h=??level x=??level or ?? level tr ut h t able 1. s h if t r egi s ter s e c tio n clk h or l shift register operation data is shifted. no changes. t rut h t abl e x h h l h l l l output all ? h l latch? data output.
bi-cmos & dmos 32bit serial-input latched driver m 566 93f p/g p mitsubishi hvo 1 ?32 output driver (push-pull) function pin name pi n f unct i o n d escri p t i o n v dd lgnd v h pgnd clk sin sout lat blk serial data output latch input. when the latch is set to ?? the data in the shift resister will enter the each latch circuit. when the latch input is set to ?? the data will be held. enable input for output control. when the blk input is set to ?? data in the latch circuit will appear at outputs. when the blk input is set to ?? all outputs will be set to ?? logic stage supply voltage logic stage ground output stage supply voltage output stage ground clock input for the internal shift resister. the data enter the internal shift resisters and the data in the shift registers wi ll be shifted in order by high to low change of the clock. serial data input logic inputs voltage outputs voltage power dissipation range storage temperature range logic outputs voltage logic stage supply voltage output stage supply voltage vi v hv o tstg -0.3 ? 120 v o -0.3 ? v dd +0.3 v dd -0.3 ? 7 v h pd -0.3 ? v dd +0.3 -0.3 ? v h -55 ? 150 940 high supply voltage output pin symbol ratings unit parameter conditions abs o l ut e m axi m um rat i ng s (ta=25 c, unless otherwise noted) v v v v v c mw ta 25 c data output 3.1 high supply voltage output pin v -2 -100 sin, lat, clk blk v th v tl output protect operating voltage i hvoh h?output current v oh v ol logic output voltage v hvoh driver output voltage v hvol i h supply current 2 operating temperature supply voltage supply voltage topr 10 ? 110 v dd 4.5 ? 5.5 v h -20 ? 75 symbol ratings unit parameter conditions rec o m m e nde d o perat i n g c o ndi t i o n s v v c limits min. typ. max. symbol test conditions unit parameter el ect r i cal charact eri s t i cs (v dd =5v, v h =110v and ta=25 c, unless otherwise noted) i dd i hvol supply current 1 l?input current l?output current i oh = -0.1ma 100 4.5 1 0 2 0 -20 106 4.95 3.4 2 50 4 2 ma ma v v i ih i il ??input current no load output all ?? no load i hvoh = -0.5ma i hvol = 0.5ma v ih =5v input pin i ol = 0.1ma high supply voltage output pin v il = 0v 02 m a 0.7 0.04 -1 1 0.4 m a m a v ma ma -3 3 m a output all ?? no load
bi-cmos & dmos 32bit serial-input latched driver m 566 93f p/g p mitsubishi ro = 220k w co = 50pf driver output propagation time tplh(so) logic output propagation time limits min. typ. max. symbol test conditions unit parameter sw i t chi ng chara ct e r i s t i cs (v dd =5v, v h =110v and ta=25 c, unless otherwise noted) fclk tphl(so) t p hl ( o ut) trout tfout clock frequency driver output rise and fall time duty = 45 ? 55% 120 100 0.16 1.3 0.35 8 300 300 mhz ns ns tp l h ( o u t ) cl = 15pf 1 m s co ro t est ci rcui t pg dut cl 50 w sout hvon v h v dd input (1) pulse generator characteristics tr 20ns tf 20ns (2) capacitance cl includes connection floating capacitance and probe input capacitance. : ro=220k w : co=50pf 2 1 2.5 2 m s m s m s t i m i ng wav e f o rm sout hvon sin blk clk 1/fmax th tsu tfso trso tr out tf out t plh(out) 50% 50% 50% 50% 50% 50% t phl(so) 50% 50% 50% t phl(out) 90% 10% 90% 50% 10% t plh(so) 90% 10% 90% 10% 50%
bi-cmos & dmos 32bit serial-input latched driver m 566 93f p/g p mitsubishi note output current i oh (ma) 10 9 8 7 6 5 4 3 2 1 1 14 16 24 32 13 0 duty cycle vs permissible output current 1 8 9 16 24 32 output current i oh (ma) 20 60 80 100 40 20 100 60 80 40 t ypi cal charact eri s t i cs thermal derating t emperature ta ( c) power dissipation pd (w) 1.0 0.94 0.5 0 100 75 50 25 0 driver output v on ? oh 0 2 4 6 8 10 02 46 8 1 0 ??output voltage v on (v) ??output current i oh (ma) ta= - 20 c ta=+25 c ta=+75 c duty cycle vs permissible output current duty cycle (%) duty cycle (%) note ta=25 c repeated frequency >100hz figure i n the circle represents the number o f concurrently operating output circuits. current value denotes a numerical value per circuit. note ta=75 c repeated frequency >100hz figure i n the circle represents the number o f concurrently operating output circuits. current value denotes a numerical value per circuit. 1. 2. 3. v dd =5v and v h =110v, unless otherwise noted thermal derating characteristics represent those of an individual ic unit. allowable duty cycle output current characteristics represent that when a standard substrate is mounted. (standard substrate: 70x70x1.6mm glass epoxy) 0 10 9 8 7 6 5 4 3 2 1 0 0
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